The present invention relates to a method for programming and for testing a select non-volatile memory cell of a memory array to store a plurality of multibit states (wherein a bit state has two states) with each state controlling a different amount of current flowing in a channel of the memory cell. More particularly, the present invention relates to a method and apparatus for programming and testing such a cell more rapidly than the method of the prior art.
Non-volatile memory cells of the EEPROM type or flash variety are well known in the art. There are at least two general types of such non-volatile memory using a floating gate to store the charges thereon to control the flow of current in a channel beneath the floating gate. One type is the stack gate wherein a control gate lies on top of a floating gate and is mutually aligned with the edges of the floating gate. The stack gate can be used in a NAND-type configuration or a NOR-type configuration. The other type of floating gate non-volatile memory cell (xe2x80x9csplit gatexe2x80x9d) uses a control gate laterally spaced from the floating gate to control the flow of current in a different portion of the channel.
In both of these types of non-volatile memory cells, it is well known to use them to store a plurality of multibit states. Thus, a single cell can store a plurality of bits. In such event, the floating gate must store a varied amount of charges with the varied amount of charges controlling a varied amount of current in the channel.
Typically, to program a non-volatile memory cell of either the stack gate type or the split gate type, charges are first all removed or erased from the floating gate. Thereafter, charges are incrementally programmed and stored on the floating gate. In the prior art, as exemplified by U.S. Pat. No. 5,293,560; or U.S. Pat. No. 5,969,987; or U.S. Pat. No. 5,901,089; or U.S. Pat. No. 5,905,673, it is disclosed that a small pulse of current is used to program the cell, to place charges onto the floating gate. Thereafter, the state of the programming of the floating gate is determined by reading the cell and comparing it to the desired state. If there is insufficient charges on the floating gate, an incrementally increased second pulse of charge is introduced and is programmed onto the floating gate. The cell is then again read and compared to the desired state. This process continues until the desired amount of charges is stored on the floating gate. Further, this process of incrementally charging the floating gate with a small pulse is used even if the floating gate is to be fully charged to a state such that the minimal amount of current flows in the channel. This is because in the prior art, especially for the NAND configuration, it is undesirable to over-program the cell. When the cell is over-programmed, the programming of other non-volatile memory cells in the same string or chain of NAND cells can be interrupted and disabled. Thus, the prior art teaches incrementally programming each cell for programming and testing purposes even if the state to which the cell is programmed is to be the fully programmed state. Because the state of the cell is checked after each pulse of programming, the checking or the reading of the cell and comparing it to the desired state is time consuming.
Accordingly, in the present invention, a method of programming or testing a select non-volatile memory cell is disclosed. A pulse generator circuit is integrated with the memory array and the memory cell has a floating gate for storing charges therein to control the flow of current in a channel. The method of programming or testing the select memory cell to one of a plurality of bit states with each state controlling a different amount of current flowing in the channel with a first state of the select memory controlling the least amount of current flowing in the channel, comprises receiving a plurality of binary signals followed by converting the plurality of binary signals into a select state of the plurality of bit states for the select memory cell. A first pulse type is generated by the pulse generator and applied in the event the select state is the first state. The select memory cell is read. The first pulse type is reapplied to the memory cell in the event that the select memory cell is not programmed to the select state. Alternatively, a second pulse type is generated by the pulse generator and is applied in the event the select state is other than the first state. The second pulse type is smaller than the first pulse type. The memory cell is then read. The second pulse type is reapplied to the select memory cell in the event the select memory cell is not programmed to the select state.
The present invention also comprises an integrated non-volatile memory cell device having an array of non-volatile memory cells and with a pulse generator circuit integrated with the array. The pulse generator circuit is capable of generating a first pulse type and a second pulse type with a second pulse type smaller than the first pulse type. The programming circuit programs a select non-volatile memory cell from the memory array to a select state where the programming circuit causes the pulse generator circuit to generate the first pulse type in the event the select state is the first state and causes the pulse generator circuit to generate the second pulse type in the event the select state is other than the first state.